In high frequency (e.g. microwave) applications, through wafer via holes are used for grounding purposes so as to effectively distribute the ground connections throughout the device. That is, through wafer vias operate to distribute as much as possible the ground signal connections throughout the whole device. However, in low frequency applications, (e.g. under 2.5 Ghz) such grounding typically occurs via bond wires which connect to the package of an IC chip. In designing field effect transistors (FETs) for applications where frequencies are low (e.g. &lt;2.5 GHz) and through-wafer vias are not used due to cost reasons, manufacturers optimize the FET topology for minimum source inductance. An example of this type of prior art device is the Philips CGY2030 3 volt, 0.5 watt 1900 MHz radio frequency power amplifier shown in FIG. 1.
This optimization results in a configuration where the source fingers 30' lead directly to the edge of the chip where bond wires connect the source fingers directly to ground without an on-chip bus, in an attempt to minimize source inductance. The gate fingers 40' are bussed and center-fed. The drain fingers 50' are also bussed together and cross over both the source and gate connections.
It is well known that drain lines and source lines carry large currents. Accordingly, handling these large currents requires relatively thick metallization layers. Unfortunately, thick metal traces cannot be patterned to very fine dimensions. Because of these large dimensions, making a bus connection that crosses over a thick metal requires a large space. These spaces and large connections end up determining the minimum gate finger spacing. In the prior art, the gate finger spacing is typically around 15-20 .mu.m. As illustrated in the prior art FIGS. 1 and 2, the drain lines undesirably cross over both the source and gate fingers. That is, as shown in FIG. 2, the drain fingers 50' are coupled to the drain bus 80' so that the drain, gate, and source lines cross over one another within the active region 101' of the FET device. These crossover areas are illustrated as reference numeral 75' and 77'. Accordingly, it is highly desirable to obtain a FET cell topology which eliminates crossover of the large current drain lines with the source and gate lines so as to reduce the gate finger spacing, as well as the overall size of the semiconductor device.
This invention eliminates the need to cross the drain lines over the source lines. By doing so, gate finger spacing no longer depends on design rules for thick metallization. This allows a much more compact FET layout which advantageously permits gate to gate spacing to be reduced by approximately 30% to 50% (8.6 to 12 .mu.m) from the current gate to gate spacings.